1. Field of the Invention
The present invention relates to a memory system and, in particular, to a memory system comprising a memory controller, a plurality of memory modules and a memory bus (data bus) connected to the memory controller and branching into a plurality of sub-busses, each of which is connected to one of the memory modules.
2. Description of Prior Art
The conventional structures of memory systems or memory subsystems include a memory controller and a data bus by which the memory controller is connected to a plurality of memory modules, usually from 2 (desktops) to 8 (servers). To this end, the data bus branches in a plurality of sub-busses, each of which is connected to one of the memory modules and, on the module, to one or more memory chips/devices. In operation, memory access, such as reading or writing, involves only one active module. The other modules are deactivated during access to the active module making use of stub resistors and/or field effect transistor (FET) switches.
In prior art memory systems of the above kind, parasitic parameters of the non-active modules restrict the bandwidth of the bus and/or the number of connected memory modules. The parasitic parameters include the input capacitance of the non-active modules and parasitic effects caused by unterminated trace stubs which cause reflections. Thus, the data rate in the data bus of prior art memory sub-systems, which include more than one memory module, is restricted due to the influence of the parasitic parameters of non-active module(s).